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| 1P LDC20 G1 0B/P LD C20 G1 0 fax id: 6014 PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features * Fast -- Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns -- Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns * Low power -- ICC max.: 70 mA, commercial -- ICC max.: 100 mA, military * Commercial and military temperature range * User-programmable output cells -- Selectable for registered or combinatorial operation -- Output polarity control -- Output enable source selectable from pin 13 or product term * Generic architecture to replace standard logic functions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8 * Eight product terms and one OE product term per output * CMOS EPROM technology for reprogrammability * Highly reliable -- Uses proven EPROM technology -- Fully AC and DC tested -- Security feature prevents logic pattern duplication -- 10% power supply voltage and higher noise immunity Functional Description Cypress PLD devices are high-speed electrically programmable logic devices. These devices utilize the sum-of-products (AND-OR) structure providing users the ability to program custom logic functions for unique requirements. In an unprogrammed state the AND gates are connected via EPROM cells to both the true and complement of every input. By selectively programming the EPROM cells, AND gates may be connected to either the true or complement or disconnected from both true and complement inputs. Logic Block Diagram VSS 12 I 11 I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 CP/I 1 PROGRAMMABLE ANDARRAY 8 8 8 8 8 8 8 8 8 8 OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL 13 I/OE 14 I/O 9 15 I/O 8 16 I/O 7 17 I/O 6 18 I/O 5 19 I/O 4 20 I/O 3 21 I/O 2 22 I/O 1 23 I/O 0 24 V CC 20G10-1 Pin Configurations LCC Top View STD PLCC Top View JEDEC PLCC Top View [1] I I I I I I NC 5 6 7 8 9 10 11 4 3 2 1 282726 25 24 23 PLDC20G10 22 PLDC20G10B 21 20 19 12131415161718 4 3 2 1 2827 26 NC I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I I NC I I NC 5 6 7 8 9 10 11 25 24 23 PLDC20G10 PLDC20G10B 22 21 20 121314 1516 1718 19 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I I I NC I I I 5 6 7 8 9 10 11 4 3 2 1 2827 26 25 24 23 CG7C323-A CG7C323B-A 22 21 20 121314 1516 1718 19 I/O 2 I/O 3 I/O 4 NC I/O 5 I/O 6 I/O 7 20G10-2 20G10-4 20G10-3 Note: 1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The difference is in the location of the "no connect" or NC pins. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 August 1988 - Revised March 26, 1997 PLDC20G10B/PLDC20G10 Selection Guide ICC (mA) Generic Part Number 20G10B-15 20G10B-20 20G10B-25 20G10-25 20G10-30 20G10-35 20G10-40 55 80 55 80 35 40 Com/Ind 70 70 100 100 25 30 30 35 Mil tPD (ns) Com/Ind 15 20 20 25 15 20 25 25 Mil tS (ns) Com/Ind 12 12 15 18 15 20 Mil tCO (ns) Com/Ind 10 12 15 15 Mil Functional Description (continued) Cypress PLDC20G10 uses an advanced 0.8-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent advantage of being able to program and erase each cell enhances the reliability and testability of the circuit. This reduces the burden on the customer to test and to handle rejects. A preload function allows the registered outputs to be preset to any pattern during testing. Preload is important for testing the functionality of the Cypress PLD device. tion Table and in Figures 1 through 8. A total of eight different configurations are possible, with the two most common shown in Figure 3 and Figure 5. The default or unprogrammed state is registered/active/LOW/Pin 11 OE. The entire programmable output cell is shown in the next section. The architecture bit `C1' controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is fed back to the array. This allows the creation of control-state machines by providing the next state. The register is clocked by the signal from Pin 1. The register is initialized on power up to Q output LOW and Q output HIGH. In both the combinatorial and registered configurations, the source of the output enable signal can be individually chosen with architecture bit `C2'. The OE signal may be generated within the array, or from the external OE (Pin 13). The Pin 13 allows direct control of the outputs, hence having faster enable/disable times. Each output cell can be configured for output polarity. The output can be either active HIGH or active LOW. This option is controlled by architecture bit `C0'. Along with this increase in functional density, the Cypress PLDC20G10 provides lower-power operation through the use of CMOS technology and increased testability with a register preload feature. 20G10 Functional Description The PLDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8. Thus, the PLDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin devices. It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the 20G10 is erased and then can be reprogrammed. The programmable output cell provides the capability of defining the architecture of each output individually. Each of the 10 output cells may be configured with registered or combinatorial outputs, active HIGH or active LOW outputs, and product term or Pin 13 generated output enables. Three architecture bits determine the configurations as shown in the Configura- 2 PLDC20G10B/PLDC20G10 Programmable Output Cell OE PRODUCT TERM OUTPUT ENABLE MUX C2 10 11 OUTPUT SELECT MUX D Q 00 CP 0 INPUT/ FEED- BACK MUX C3 C2 C1 C0 Q 01 C1 C0 1 PIN 13 20G10-5 Configuration Table Figure C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 Configuration Product Term OE/Registered/Active LOW Product Term OE/Registered/Active HIGH Product Term OE/Combinatorial/Active LOW Product Term OE/Combinatorial/Active HIGH Pin 13 OE/Registered/Active LOW Pin 13 OE/Registered/Active HIGH Pin 13 OE/Combinatorial/Active LOW Pin 13 OE/Combinatorial/Active HIGH 1 2 5 6 3 4 7 8 3 PLDC20G10B/PLDC20G10 Registered Output Configurations C2 = 0 C1 = 0 C0 = 0 CP D Q D Q C2 = 0 C1 = 0 C0 = 1 CP Q Q 20G10-6 20G10-7 Figure 1. Product Term OE/Active LOW Figure 2. Product Term OE/Active HIGH D Q C2 = 1 C1 = 0 C0 = 0 CP D Q C2 = 1 C1 = 0 C0 = 1 CP Q Q 20G10-8 20G10-9 Figure 3. Pin 13 OE/Active LOW Figure 4. Pin 13 OE/Active HIGH Combinatorial Output Configurations[2] C2 = 0 C1 = 1 C0 = 0 C2 = 0 C1 = 1 C0 = 1 20G10-10 20G10-11 Figure 5. Product Term OE/Active LOW Figure 6. Product Term OE/Active HIGH C2 = 1 C1 = 1 C0 = 0 C2 = 1 C1 = 1 C0 = 1 20G10-12 PIN 13 PIN 13 20G10-13 Figure 7. Pin 13 OE/Active Low Figure 8. Pin 13 OE/Active HIGH Note: 2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected 4 PLDC20G10B/PLDC20G10 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V Output Current into Outputs (LOW) ............................. 16 mA DC Programming Voltage PLDC20G10B and CG7C323B-A............................... 13.0V PLDC20G10 and CG7C323-A.................................... 14.0V Latch-Up Current ..................................................... >200 mA Static Discharge Voltage ............................................. >500V (per MIL-STD-883, Method 8015) Operating Range Range Commercial Military[3] Industrial ] Ambient Temperature 0C to +75C -55C to +125C -40C to +85C VCC 5V 10% 5V 10% 5V 10% Electrical Characteristics Over the Operating Range (Unless Otherwise Noted) [4] Parameter VOH VOL VIH VIL IIX ISC ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Leakage Current VCC = Min., VIN = VIH or VIL VCC = Min., VIN = VIH or VIL Test Conditions IOH = -3.2 mA IOH = -2 mA IOL = 24 mA IOL = 12 mA Com'l/Ind Military Com'l/Ind Military 2.0 0.8 -10 +10 -90 70 55 100 80 -100 100 V V A mA mA mA mA mA A Inputs[5] 0.5 V Min. 2.4 Max. Unit V Guaranteed Input Logical HIGH Voltage for All Inputs[5] Guaranteed Input Logical LOW Voltage for All VSS VIN VCC Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7] Power Supply Current 0 VIN VCC Com'l/Ind-15, -20 VCC = Max., Com'l/Ind-25, -35 IOUT = 0 mA Unprogrammed Device Military-20, -25 Military-30, -40 Output Leakage Current VCC = Max., VSS VOUT VCC IOZ Capacitance[7] Parameter CIN COUT Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz Max. 10 Unit pF Output Capacitance VIN = 2.0V, VCC = 5.0V 10 pF Notes: 3. TA is the "instant on" case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. 5 PLDC20G10B/PLDC20G10 AC Test Loads and Waveforms (Commercial) R1 238 (319 MIL) 5V OUTPUT 50pF INCLUDING JIG AND SCOPE R2 170 (236 MIL) INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF R2 170 (236 MIL) 20G10-14 R1 238 (319 MIL) (a) (b) Equivalent to: THEVENIN EQUIVALENT (Commercial) 99 OUTPUT 2.08V=Vthc 20G10-15 Equivalent to: THEVENIN EQUIVALENT (Military/Industrial) 136 OUTPUT 2.13V=V thm 20G10-16 Switching Characteristics Over Operating Range[3, 8, 9] Commercial B-15 Parameter tPD tEA tER tPZX tPXZ tCO tS tH tP[10] tWH tWL fMAX [11] B-20 20 20 20 15 15 12 12 0 24 10 10 41.6 15 0 30 12 12 -25 25 25 25 20 20 15 30 0 55 17 17 -35 Unit ns ns ns ns ns ns ns ns ns ns ns MHz 35 35 35 25 25 25 Description Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Pin 11 to Output Enable Pin 11 to Output Disable Clock to Output Input or Feedback Set-Up Time Hold Time Clock Period Clock High Time Clock Low Time Maximum Frequency Min. Max. Min. Max. Min. Max. Min. Max. 15 15 15 12 12 10 12 0 22 8 8 45.4 33.3 18.1 Notes: 8. Part (a) of AC Test Loads and Waveforms used for all parameters except tER, tPZX, and tPXZ. Part (b) of AC Test Loads and Waveforms used for tER, t PZX , and tPXZ. 9. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5V for an enabled HIGH output or VOL + 0.5V for an enabled LOW input. 10. tP, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tP = tS + tCO. The minimum guaranteed period for registered data path operation (no feedback) can be calculated as the greater of (tWH + tWL) or (tS + tH). 11. fMAX , minimum guaranteed operating frequency, is that guaranteed for state machine operation and is calculated from fMAX = 1/(tS + tCO). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of 1/(tWH + tWL) or 1/(tS + tH). 6 PLDC20G10B/PLDC20G10 Switching Characteristics Over Operating Range[3, 8, 9] (continued) Military/Industrial B-20 Parameter tPD tEA tER tPZX tPXZ tCO tS tH tP [10] B-25 Min. 25 25 25 20 20 15 18 0 33 14 14 30.3 20 0 40 16 16 -30 Max. 30 30 30 25 25 20 35 0 60 22 22 -40 Min. Max. 40 40 40 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns MHz Description Input or Feedback to Non-Registered Output Input to Output Enable Input to Output Disable Pin 11 to Output Enable Pin 11 to Output Disable Clock to Output Input or Feedback Set-Up Time Hold Time Clock Period Clock High Time Clock Low Time Min. Max. 20 20 20 17 17 15 Max. Min. 15 0 30 12 12 33.3 tWH tWL fMAX [11] Maximum Frequency 25.0 16.6 Switching Waveform INPUTS I/O, REGISTERED FEEDBACK tS CP tP OE tPXZ tH tW tW tCO REGISTERED OUTPUTS tPD COMBINATORIAL OUTPUTS tPZX t ER t EA 20G10-17 7 PLDC20G10B/PLDC20G10 Functional Logic Diagram 1 OE 0 0 4 8 12 16 20 24 28 32 36 40 * * * OUTPUT CELL 7 23 OE 0 * * * OUTPUT CELL 7 22 2 OE 0 * * * 7 OUTPUT CELL 21 3 OE 0 * * * OUTPUT CELL 7 20 4 OE 0 * * * OUTPUT CELL 7 19 5 OE 0 * * * OUTPUT CELL 7 18 6 OE 0 * * * OUTPUT CELL 7 17 7 OE 0 * * * OUTPUT CELL 7 16 8 OE 0 * * * OUTPUT CELL 7 15 9 OE 0 * * * OUTPUT CELL 7 14 10 11 20G10-18 13 8 PLDC20G10B/PLDC20G10 Ordering Information tPD (ns) 15 20 25 tS (ns) 12 15 15 tCO (ns) 10 15 15 ICC (mA) 70 100 55 Ordering Code PLDC20G10B-15PC PLDC20G10B-15WC PLDC20G10B-20DMB PLDC20G10-25JC PLDC20G10-25PC/PI PLDC20G10-25WC 30 20 20 80 PLDC20G10-30DMB PLDC20G10-30LMB PLDC20G10-30WMB 35 30 25 55 PLDC20G10-35JC PLDC20G10-35PC Package Name P13 W14 D14 J64 P13 W14 D14 L64 W14 J64 P13 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Windowed CerDIP 24-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 24-Lead (300-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 24-Lead (300-Mil) Molded DIP Commercial Military Commercial Commercial/ Industrial Commercial Military Operating Range Commercial MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL IIX IOZ ICC Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 tPD tPZX tCO tS tH Switching Characteristics Parameter Subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Document #: 38-00019-H 9 PLDC20G10B/PLDC20G10 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 10 PLDC20G10B/PLDC20G10 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 11 PLDC20G10B/PLDC20G10 Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D- 9Config.A (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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